Field
This disclosure relates generally to data processing systems, and more specifically, to data processing systems with a write request network and a write data network.
Related Art
A data processing system may be configured as having a plurality of nodes interconnected by a plurality of networks. Each of these nodes includes a switch point for routing signals between nodes along the networks and may include any type of device, such as a processing unit or memory. In the case of a data processing system with a shared memory, which is accessible by multiple nodes of the system, address and data portions of read and write accesses often travel independently on separate networks (i.e. on separate sets of wires). Access requests (corresponding to the address portion of an access) travel from requestor nodes to target nodes, in which the target nodes include a target memory. For a read request, read data travels from the target node to the requestor node, and for a write request, write data travels from the requestor node to the target node. In the case of multiple concurrent accesses traveling along the networks, the data processing system is vulnerable to deadlock scenarios. This may occur when the progress of write requests and write data through the networks become uncoordinated.
In one solution to avoid deadlocks, a write request is first sent to a target node. A data grant is then sent back to the requester node before the data is allowed to transfer out of the requester node towards the target node. For each write request that is granted by the target node, the target node reserves buffer resource to receive the data. The write data of the granted writes is then accepted as they arrive to the target. However, while this may avoid deadlocks, this increases latency in large systems. For example, if the target node is far from the requester node, the round trip latency from write request to write data delivery is large. Furthermore, since the requester has limited buffer resource to hold the write data, large latencies can lead to requester stalls for the write accesses. Therefore, a need exists for improved writes in shared memory systems.